1. Technical Field
The present invention relates to neural networks in general, and in particular to artificial neurons utilized within a neural network. Still more particularly, the present invention relates to a neuron circuit employed as a building block of a neural network that can be implemented in an integrated circuit.
2. Description of the Prior Art
Artificial neural networks are utilized in a wide variety of applications, such as speech recognition, process control, optical character recognition, signal processing, image processing, etc. Generally speaking, an artificial neural network is made up of multiple elemental processing blocks called neuron circuits. Thus, a neuron circuit is the fundamental building block of a neural network.
Referring now to the drawings and in particular to FIG. 1a, there is depicted a block diagram of a conventional neuron circuit. As shown, a neuron circuit 10 includes inputs x1 through xn weighted by respective synapses w1 through wn, which are accumulated together by a summing circuit 11. The output of summing circuit 11 is then fed into a non-linear circuit 12 for generating an output 15. In this example, the non-linear transfer function of non-linear circuit 12 is in the form of a sigmoid-shaped function that can be expressed as follows:
xe2x80x83output=1/(1+exe2x88x92NET)
Many different types of non-linear transfer function can be utilized within non-linear circuit 12. For example, the non-linear transfer function can be a binary threshold function 16 having a binary threshold, as shown in FIG. 1b. 
In sum, a conventional neuron circuit requires a circuit for weighted input connections, a summing circuit, a multiplier circuit, and a circuit for performing a non-linear function. Because of the total size of the above-mentioned circuits, the number of conventional neuron circuits that can be manufactured on a semiconductor device is severely limited, not to mention the response time is relatively slow. Consequently, it would be desirable to provide an improved neuron circuit that is fast, simple, and inexpensive to implement.
In accordance with a preferred embodiment of the present invention, a neuron circuit that can be served as a building block for a neural network implemented in an integrated circuit includes a synapse circuit block and a neuron body circuit block. The synapse circuit block has three transistors, and the body of one of the three transistors is controlled by a weighted input. The neuron body circuit block includes a current mirror circuit, a summing circuit, and an invertor circuit. The neuron body circuit is coupled to the synapse circuit block to generate an output pulse.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.